The present invention relates to an image pickup circuit.
In the recent years, solid-state image pickup devices such as CMOS (complementary metal oxide semiconductor) sensors have been widely implemented to portable telephones, compact digital cameras, high-class single-lens reflex cameras, camcoders, monitor cameras and guide apparatuses.
Recently, there has been developed a high performance sensor including an on-chip processing blocks such as an image processing circuit together with a CMOS sensor to thereby output high quality images.
For example, sensors employing column-parallel A/D (analog to digital) conversion method (hereinafter referred for convenience to as “column AD method”) have been proposed.
In the column AD method, an A/D converter is provided for every column of pixels (hereinafter referred to as a “column” where appropriate), and the pixel signals (analog signals) of individual pixels for the respective columns are read by one operation and then A/D converted directly.
Further, the column AD method employs parallel processing for every horizontal line in an image, thus eliminating the necessity for high-frequency horizontal scanning. This enables the A/D conversion to be performed vertically at a low frequency, making it easy to separate signal components and noise components generated in a high frequency band.
The configuration of a solid-state image pickup device employing the column AD method will be described here with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram showing the configuration of an example of the solid-state image pickup device employing the column AD method.
In FIG. 1, a solid-state image pickup device 11 includes a vertical scanning circuit 21, a pixel array 22, vertical signal lines 231 to 23N (N is a positive integer), current sources 241 to 24N, a slope generating circuit 25, comparators 261 to 26N, and counters 271 to 27N.
Under control of the controller (not shown), the vertical scanning circuit 21 supplies sequentially output control signals for controlling the outputs of pixel signals to vertically aligned pixels 221 to 22N in the pixel array 22 at a predetermined timing.
The pixel array 22 is composed of a plurality of pixels arranged in a matrix. FIG. 1 shows the pixels 221 to 22N disposed in a horizontal direction for one line, with the vertically aligned pixels omitted. In the pixel array 22, the individual pixels 22n which are vertically aligned output sequentially a pixel signal on the basis of the output control signal supplied from the vertical scanning circuit 21.
In the pixel array 22 of FIG. 1, the N pixels 221 to 22N are disposed horizontally (horizontal direction). The pixels 22n (n=1, 2, . . . , N) photoelectrically convert the incident light, and output the pixel signal of a voltage corresponding to the light. These pixels 221 to 22N are connected to the N vertical signal lines 231 to 23N, respectively, and the pixel signals outputted from the pixels 221 to 22N are supplied through the vertical signal lines 231 to 23N to one of two input terminals in each of the N comparators 261 to 26N, respectively. The pixels 221 to 22N are also grounded through the N current sources 241 to 24N, respectively.
The slope generating circuit 25 supplies a slope signal, whose voltage drops (or rises) at a constant slope from a predetermined initial voltage, to the other of the two input terminals in each of the N comparators 261 to 26N, respectively.
The comparators 261 to 26N compare the pixel signals supplied from the pixels 221 to 22N, and the slope signal supplied from the slope generating circuit 25, and supply comparative signals representing the comparison results to the N counters 271 to 27N, respectively.
The counters 271 to 27N count a predetermined clock signal on the basis of the comparative signals supplied from the comparators 261 to 26N, respectively, and supply the count values to the circuit of the subsequent stage (not shown). In the circuit of the subsequent stage, pixel data (pixel values) are outputted on the basis of the count values supplied from the counters 271 to 27N.
In FIG. 1, the slope generating circuit 25, the comparators 26n, and the counters 27n constitute the A/D converter.
The solid-state image pickup device 11 thus configured necessitates the counters corresponding to the number N of the columns, thereby increasing the circuit area and power consumption.
FIG. 2 is a block diagram showing the configuration of other example of the solid-state image pickup device employing the column AD method.
In FIG. 2, the same references have been used as in FIG. 1 for similar components, and the description thereof is omitted.
In FIG. 2, a solid-state image pickup device 31 includes a vertical scanning circuit 21, a pixel array 22, vertical signal lines 231 to 23N, current sources 241 to 24N, a slope generating circuit 25, comparators 261 to 26N, a counter 41, and latch circuits 421 to 42N.
Each of the comparators 261 to 26N supply comparative signals representing the comparison results, to the N latch circuits 421 to 42N, respectively. The comparative signals are obtained by comparing the pixel signals supplied from the pixels 221 to 22N and the slope signal supplied from the slope generating circuit 25.
The counter 41 counts a predetermined clock signal and supplies the count value to the latch circuits 421 to 42N, respectively.
The latch circuits 421 to 42N store the count values counted by the single counter 41 in response to the comparative signals from the comparators 261 to 26N, and supply the stored count values to the circuit of the subsequent stage (not shown). In the circuit of the subsequent stage, pixel data are outputted on the basis of the count values supplied from the latch circuits 421 to 42N.
In FIG. 2, the slope generating circuit 25, the comparators 26n, the counter 41, and the latch circuits 42n constitute the A/D converter.
The solid-state image pickup device 31 thus configured can reduce the number of counters to only one, namely the counter 41.
However, when the single counter 41 is provided as in the solid-state image pickup device 31, a greater distance between the counter 41 and the latch circuit 42n causes a greater delay in counted pulse indicating the count value supplied from the counter 41 to the latch circuit 42n, due to wire resistance and wire capacity. Consequently, between the column of the latch circuit 42n having a short distance to the counter 41, and the column of the latch circuit 42n′ (n′=1, 2, . . . , N) having a long distance to the counter 41, a difference resulted from wire resistance and wire capacity occurs in pixel data outputted, thereby adversely affecting image quality.
There are also those having a plurality of arrangements that an A/D converter (a comparator and a counter) is shared among a plurality of columns (for example, see Japanese Unexamined Patent Application Publication No. 2006-80861 hereinafter referred to as Patent Document 1).
However, in the configuration of the Patent Document 1, the pixel signals of a plurality of columns are serially transmitted to be A/D converted, thus lowering the transmission rate. The counter is required to operate for a number of columns, and the power consumption thereof becomes the same as the power consumption when each of the columns has a counter.